1. Field of the Invention
This invention relates to the field of charge pump circuits, and to integrated circuits using charge pumps to produce on-chip voltages outside the range of the off-chip voltage supply.
2. Description of the Related Art
A charge pump generates a great deal of power supply and ground noise at times when peak currents drive the charge pump. In the event that the power supply line or the ground line is shared between the charge pump and another analog circuit block on the same chip, the other analog circuit block will suffer from the power supply or ground noise generated by the charge pump. Further, flash memory architecture and mixed mode integrated circuit architecture often has a power supply or ground line shared between a charge pump and another analog circuit block. What is needed is a charge pump that generates less power supply and ground noise, especially when the power supply line and/or the ground line is shared between the charge pump and another analog circuit.
FIG. 1 illustrates a block diagram of a charge pump 100. In FIG. 1, clock signal circuitry 200 provides pump timing signals 210 to a pump timing circuit 300. Pump timing circuit 300 provides amplified pump timing signals to pump stages 400. Pump timing circuit 300 is coupled to a voltage supply 302 and a ground 304.
FIG. 2 schematically illustrates the pump timing circuit 300. The pump timing circuit 300 includes four series of inverters: a first inverter series 310, a second inverter series 330, a third inverter series 350, and a fourth inverter series 370.
The first inverter series 310 includes an input 312, a first inverter 314, a second inverter 316, a third inverter 318, a fourth inverter 320, and an output 322. The input 312 is connected to the input of the first inverter 314. The first inverter 314, the second inverter 316, the third inverter 318, and the fourth inverter 320 are connected in series. The output of the fourth inverter 320 is connected to the output 322. The output 322 provides an amplified first pump clock signal 324.
The second inverter series 330 includes an input 332, a fifth inverter 334, a sixth inverter 336, a seventh inverter 338, an eighth inverter 340, and an output 342. The input 332 is connected to the input of the fifth inverter 334. The fifth inverter 334, the sixth inverter 336, the seventh inverter 338, and the eighth inverter 340 are connected in series. The output of the eighth inverter 340 is connected to the output 342. The output 342 provides an amplified second transfer clock signal 344.
The third inverter series 350 includes an input 352, a ninth inverter 354, a tenth inverter 356, an eleventh inverter 358, a twelfth inverter 360, and an output 362. The input 352 is connected to the input of the ninth inverter 354. The ninth inverter 354, the tenth inverter 356, the eleventh inverter 358, and the twelfth inverter 360 are connected in series. The output of the twelfth inverter 360 is connected to the output 362. The output 362 provides an amplified second pump clock signal 364.
The fourth inverter series 370 includes an input 372, a thirteenth inverter 374, a fourteenth inverter 376, a fifteenth inverter 378, a sixteenth inverter 380, and an output 382. The input 372 is connected to the input of the thirteenth inverter 374. The thirteenth inverter 374, the fourteenth inverter 376, the fifteenth inverter 378, and the sixteenth inverter 380 are connected in series. The output of the sixteenth inverter 380 is connected to the output 382. The output 382 provides an amplified first transfer clock signal 384.
The following table details the length and width dimensions of the p-channel and n-channel transistors for some of the inverters in the pump timing circuit 300.
FIG. 3 schematically illustrates pump stages 400. Pump stages 400 includes an input 410, a first stage 430, a second stage 450, a third stage 470, a diode 490, and an output 420. The input 410, the first stage 430, the second stage 450, the third stage 470, the diode 490, and the output 420 are connected in series. The input 410 is 110 coupled to the voltage supply 302 (VDD) and the first stage 430.
The first stage 430 includes a first transistor 432, a second transistor 436, a first transfer capacitor 438, and a first pump capacitor 442. The first transistor 432 is an n-channel transistor having a gate, a source connected to node 434, and a drain connected to the input 410. The second transistor 436 is an n-channel transistor having a gate connected to node 434, a source connected to the gate of the first transistor 432, and a drain connected to the drain of the first transistor 432. The first transfer capacitor 438 is a capacitor-connected n-channel transistor having a first terminal connected to the fourth inverter series output 382 and a second terminal connected to the gate of the first transistor 432. The first pump capacitor 442 has a first terminal connected to the first inverter series output 322 and a second terminal connected to node 434.
The second stage 450 includes a third transistor 452, a fourth transistor 456, a second transfer capacitor 458, and a second pump capacitor 462. The third transistor 452 is an n-channel transistor having a gate, a source connected to node 454, and a drain connected to node 434. The fourth transistor 456 is an n-channel transistor having a gate connected to node 454, a source connected to the gate of the third transistor 452, and a drain connected to the drain of the third transistor 452. The second transfer capacitor 458 is a capacitor-connected n-channel transistor having a first terminal connected to the second inverter series output 342 and a second terminal connected to the gate of the third transistor 452. The second pump capacitor 462 has a first terminal connected to the third inverter series output 362 and a second terminal connected to node 454.
The third stage 470 includes a fifth transistor 472, a sixth transistor 476, a third transfer capacitor 478, and a third pump capacitor 482. The fifth transistor 472 is an n-channel transistor having a gate, a source connected to node 474, and a drain connected to node 454. The sixth transistor 476 is an n-channel transistor having a gate connected to node 474, a source connected to the gate of the fifth transistor 472, and a drain connected to the drain of the fifth transistor 472. The third transfer capacitor 478 is a capacitor-connected n-channel transistor having a first terminal connected to the fourth inverter series output 382 and a second terminal connected to the gate of the fifth transistor 472. The third pump capacitor 482 has a first terminal connected to the first inverter series output 322 and a second terminal connected to node 474.
Diode 490 is a diode-connected n-channel transistor having a first terminal connected to node 474 and a second terminal connected to the pump stages output 420.
Heretofore, the requirement for a charge pump with less power supply noise and less ground noise has not been fully met. What is needed is a solution that simultaneously addresses both of these requirements.
A primary goal of the invention is to provide a charge pump that has less power supply noise. Another primary goal of the invention is to provide a charge pump having less ground noise. Another primary goal of the invention is to provide a charge pump which overcomes inefficiencies of older designs.
A charge pump comprises a first timing circuit supplying a timing signal from a timing signal output and each of the charge pump stages receive a timing signal via a capacitor, charge is pumped to an output in response to a timing signal made of two components separated by a delay. Current usually flows in the same direction during both components of the timing signal, and the power of the timing signal increases from the onset of the second component. The power of the timing signal increases due to the use of the second component to couple the capacitor to a voltage source, a current source, or a ground.
According to another aspect of the invention, the charge pump pumps charge in response to several timing signals. In a preferred embodiment, the onsets of the first and second components are defined by distinct edges of the timing signals. The onsets can be defined by several clock signals.
In another aspect of the invention, two transistors and two capacitors form a charge pump boost stage. In a preferred embodiment, two clock signals drive one of the capacitors. An amplification circuit can increase the power of one or both of the clock signals, and a diode can be coupled to the output of the charge pump.
In further aspects of the invention, a second charge pump stage is added and a third charge pump stage is added to define a four-phase charge pump. In yet further aspects of the invention, one or both of two transfer clock signals can be used to drive one or more of the pump capacitors in the four-phase charge pump. According to yet other aspects of the invention, an integrated circuit is provided including the charge pump on a single chip.
A method for reducing a magnitude of a peak current flowing in a charge pump comprises driving a charge pump node with a first timing signal having a polarity, and driving the node with a second timing signal having the polarity, such that the onsets of the first and second timing signals are separated by a delay. Another method for reducing a magnitude of a peak current flowing in a charge pump comprises driving a charge pump node by activating a current handling device coupled the node through a capacitor, and after a delay, driving the node by activating a second current handling device coupled to the node through the capacitor, while the first current handling device remains activated.